1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to encoding of signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs turbo codes. Another type of communication system that has also received interest is a communication system that employs LDPC (Low Density Parity Check) code. A primary directive in these areas of development has been to try continually to lower the error floor within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR (Signal to Noise Ratio), that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
LDPC code has been shown to provide for excellent decoding performance that can approach the Shannon limit in some cases. For example, some LDPC decoders have been shown to come within 0.3 dB (decibels) from the theoretical Shannon limit. While this example was achieved using an irregular LDPC code of a length of one million, it nevertheless demonstrates the very promising application of LDPC codes within communication systems.
FIG. 6 is a diagram illustrating an embodiment of a prior art MLC (Multi-Level Code) encoder 600. Such a coded modulation scheme using MLC was introduced by Imai and Hirakawa as described in the following reference.
H. Imai and S. Hirakawa, “A new multilevel coding method using error correcting codes,” IEEE Trans. Inform. Theory, Vol. IT-23, pp. 371–377, May 1977.
Information bits are provided to a data partitioner 610 and subsequently provided to a plurality of encoders, shown as encoder 1 621, encoder 2 622, and encoder 3 623. Corresponding encoded bits are output from each of the encoders, and they are provided to a symbol mapper 630. A sequence of discrete valued modulation symbols is output from the symbol mapper 630. In this prior art embodiment, each of the symbols within the sequence of discrete valued modulation symbols is mapped according to the same constellation shape and mapping of the constellation points included therein.
The main goal of using MLC is to optimize the code in Euclidean space rather than dealing with Hamming distance in similar fashion as is performed within TCM (Trellis Coded Modulation). A good description of TCM is provided by Ungerboeck in the following reference.
G. Ungerboeck, “Channel coding with multilevel/phase signals,” IEEE Trans. Inform. Theory, Vol. IT-28, pp. 55–67, Jan. 1982. In an MLC scheme, typically either Gray code map or Ungerboeck mapping (or labeling) is used.
FIG. 7 is a diagram illustrating an embodiment of prior art MSD (Multi-Stage Decoding) of a level 3 code 700. In order to decode MLC (as also described by Imai and Hirakawa—see reference cited above), a MSD (Multi-Stage Decoding) approach as depicted in FIG. 7 may be employed.
A received I, Q value r 701 is provided simultaneously to a decoder 1 711, a delay element 723, and a delay element 725. The output from the decoder 1 711 is provided to a decoder 2 712, and the output from the decoder 2 712 is provided to a decoder 3 713. The decoding (i.e. prior art MSD of the level 3 code 700) has three parallel paths. Specifically, the output from the decoder 1 711 is also provided to a delay element 721. The output from the delay element 723 is also provided to the decoder 2 712. The output from the delay element 725 is also provided to the delay element 726. The output from the delay element 721 is also provided to the delay element 722. The output from the decoder 2 712 is also provided to a delay element 724. The output from the delay element 726 is also provided to the decoder 3 713.
The MSD approach of this embodiment is in fact a straightforward consequence of the chain rule of Shannon mutual information when the decoder is not implemented in an iterative manner. However, this MSD approach can inherently cause significant time delay as indicated in FIG. 7.
FIG. 8 is a diagram illustrating an embodiment of prior art iterative PID (Parallel Independent Decoding) 800. In this embodiment, a received I, Q value r 801 is simultaneously provided to three separate and parallel operating decoders, shown as a decoder 1 811, a decoder 2 812, and a decoder 3 813. Each of these parallel operating decoders decodes the received provides best estimate of the information bits encoded therein.
As described in the following reference, Wachsmann provides for a suboptimal decoding method that is described as PDL (Parallel independent Decoding of the individual Levels) (this decoding approach is depicted in FIG. 8).
U. Wachsmann, R. F. H. Fischer and J. B. Huber, “Multilevel codes: theoretical concepts and practical design rules,” IEEE Trans. Inform. Theory, Vol. 45, pp. 1361–1391, July 1999.
The name PDL is simplified to PID (Parallel Independent Decoding) by Hou, et al., as described in the following reference.
J. Hou, P. H. Siegel, L. B. Milsten and H. D. Pfister, “Capacity-approaching bandwidth efficient coded modulation schemes based on low-density parity-check codes,” IEEE Trans. Inform. Theory, Vol. 49, pp. 2141–2155, September 2003.
Wachsmann (see reference above) shows that the gap between MSD and PID is small if Gray code mapping is used. Wachsmann (see reference above) used turbo code in every level to obtain a better performance of the MLC.
FIG. 9 is a diagram illustrating an embodiment of prior art iterative MSD of a level 3 code 900. This embodiment is somewhat similar to the prior art MSD of the level 3 code 700 of a level 3 code depicted in the FIG. 7.
A received I, Q value r 901 is provided simultaneously to a decoder 1 911, a delay element 923, and a delay element 925. The output from the decoder 1 911 is provided to a decoder 2 912, and the output from the decoder 2 912 is provided to a decoder 3 913. The decoding (i.e. iterative MSD 900) has three parallel paths as well as iterative decoding feedback signals. Specifically, the output from the decoder 1 911 is also provided to a delay element 921. The output from the delay element 923 is also provided to the decoder 2 912. The output from the delay element 925 is also provided to the delay element 926. The output from the delay element 921 is also provided to the delay element 922. The output from the decoder 2 912 is also provided to a delay element 924. The output from the delay element 926 is also provided to the decoder 3 913.
However, this prior art iterative MSD of the level 3 code 900 differs from the MSD of the level 3 code 700, in that, iterative decoding feedback signals are provided to selected functional blocks. For examples, the output of the decoder 1 911 that is provided to the decoder 2 912 is also provided to the decoder 3 913. In addition, the output from the decoder 2 912 that is provided to the decoder 3 913 is also fed back to the decoder 1 911. Similarly, the output from the decoder 3 913 is fed back as input to each of the decoder 1 912 and the decoder 2 912. The iterative decoding approach of this embodiment allows the MSD of the level 3 code 900 to have performance improvement over the MSD of the level 3 code 700.
FIG. 10 is a diagram illustrating an embodiment of prior art iterative PID of a level 3 code 1000. For an MLC with turbo component codes (i.e., each of the individual encoders are turbo encoder), an iterative MSD (IMSD) (as also described by Worz and Hagenauer, see cited references below), or Iterative Parallel Independent Decoding (IPID) is used.
T. Worz and J. Hagenauer, “Iterative decoding for multilevel codes using reliability information,” in Proc. IEEE Global Telecoms. Conf. (GLOBECOM) (Orlando, Fla., December 1992).
P. A. Martin and D. P. Taylor, “On multilevel codes and iterative multistage decoding,” IEEE Trans. Inform. Theory, Vol. 47, pp. 1916–1925, November 2001.
In this diagram, a received I, Q value r 1001 is provided simultaneously to 3 different decoders shown as a decoder 1 1011, a decoder 2 1012, and a decoder 3 1013. Each of the individual decoders in this embodiment provides feedback signals to assist in the corresponding iterative decoding performed therein. As can be seen, each of the decoders in this IPID embodiment does in fact operate independently on the received I, Q value r 1001.
In the Hou reference (see cited reference above), modulation with ML LDPC (Multi-Level Low Density Parity Check) code is studied, where the performance difference between IMSD and iterative IPID is discussed. It is also shown in that same paper that the gap between the performance of the IMSD and IPID is about 0.07 dB when Gray code mapping is used.
FIG. 11 is a diagram illustrating an embodiment of prior art BICM (Bit Interleaved Coded Modulation) 1100 that is employed in conjunction with LDPC (Low Density Parity Check) coding and modulation encoding. This is yet another class of coded modulation scheme, namely, BICM as described by Caire in the following reference and also as depicted in FIG. 11.
G. Caire, G. Taricoo, and E. Biglien, “Bit-interleaved coded modulation,” IEEE Trans. Inform. Theory, Vol. 44, pp. 927–946, May. 1998.
In that scheme, only Gray code map works. However, if the signal mapping method is not restricted MLC, then the performance is better than BICM, as is also described by Wachsmann (see reference above).
This embodiment of BICM 1100 operates by performing direct combining of bit encoding and modulation encoding, with the exception that an π (interleaver) 1120 is interposed between a bit encoder 1110 and a modulation encoder 1130.
A binary sequence (e.g., a bit stream of information bits) is provided to the bit encoder 1110 from which encoded bits are output. The bit encoder 1110 introduces a degree of redundancy (or parity) within the bit sequence (i.e., the information bits) provided thereto. The encoded bits output from the bit encoder 1110 may be systematic or non-systematic in nature.
These encoded bits are then provided to the π (interleaver) 1120 to generate a degree of randomness within the coded bits thereby (hopefully) making that coded bit sequence to be more robust to interference, noise, and other deleterious effects. This coded bit sequence that has been interleaved is then provided to a S/P (Serial to Parallel) path (i.e., shown as a bit to m-bit symbol transformation 1121) such that the output symbols may be provided to the modulation encoder 1130. Again, this S/P path performs the bit to m-bit symbol transformation. The modulation encoder 1130 outputs a signal sequence that includes symbols (composed of the interleaved coded bits) that correspond to a modulation having a constellation and a corresponding mapping.
In the art of encoding of signals to be employed within communication systems, there is an ever continual need to provide means by which improved performance may be achieved in trying to reach the ultimate goal of Shannon's limit within a communication channel while operating at a particular SNR. As such, there is a need in the art to provide better means by which encoded signal may be generated for use in communicating information across a communication channel.